My Humble House

[Solution] 
This warning happens when the upper module instantiates this sub module and defines its parameters by defparam at the same time:

To solve this problem caused by large memory consumption in Windows, the following command can be used to increase the user-mode virtual address space:
 

在 nTrace 視窗直接按 x 鍵可以把目前 nWave 游標所在時間的所有 signal 的 value 顯示在 signal 下方.
 
Active Annotation in Source Window

Use Source ->Active Annotation (or press x key in nTrace window) to annotate simulation result to source window.
It will annotate the signal values at the cursor time and display the values under each signal.
It will also display signal transition.
Any signals can be annotated if they are dumped, no matter whether their waveform are displayed

Solution:
把 [x : y] 的 range 語法改成 [x +: width] 或 [x -: width]
 
Reason:

這是因為有些 Verilog module 並沒有指定 timescale. 可以在 ncelab 指令中加入 -timescale 1ns/10ps 來指定預設的timescale, 或是在所有 Verilog module 前都指定 timescale.