Ex 1. The path from FF1 to FF2 is designed to take 2 clock cycles rather than 1.
set_multicycle_path -setup 2 \
目前分類：Verilog (1)
- Feb 13 Thu 2014 15:13
[Verilog] Multicycle path setting in Design Compiler
Ex 1. The path from FF1 to FF2 is designed to take 2 clock cycles rather than 1.
set_multicycle_path -setup 2 \
